March 03, 2016 @ 11:00 am - 12:00 pm
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Mirabilis Design Inc - Ranjith K R
Mirabilis Design Inc - Deepak Shankar
Avionics industry is trying to replace numerous separate processors and line replaceable units (LRU) with fewer and more centralized processing units; which is coined the Integrated Modular Avionics (IMA). The IMA architecture give rise to many inter-related decisions that must be made by system architects, such as how to assign software to hardware processors, amount of power consumed for each use-cases, reduce risk, schedule the tasks to the ARINC 653 virtual machines, and determine the network bandwidth for the selected workload and processing. We at Mirabilis Design worked with over 20 avionics divisions and this Webinar is based on our experience.
During this webinar we will be talking about the challenges in IMA architectures and how these challenges can be addressed using early design exploration. During this presentation, we will start with aggregating the reference document; model the hardware, workload, ARINC 653; run simulation; and conduct analysis. We will show you how to make the decision based on simulation data. Other concepts includes; injecting faults to study the system behavior, as graceful degradation of a subsystem and the dependency across the system; End-to-End latency and impact of I/O data rates.
Why attend this webinar:
1. Challenges involved in IMA architectures and the role of early design exploration
2. Showcase of the reference document, model the hardware, workload, ARINC 653, run simulation and conduct analysis.
3. Process of decision-making based on simulation data.
More information about the speakers:
Mirabilis Design Inc - Ranjith K R - Senior Application Engineer
Knowledge of FPGA and ASIC Design Flow, knowledge of Architecture Exploration and System Performance analysis, knowledge of Model Based System development at different levels of abstractions such as Statistical level, Macro Architecture level and Cycle Accurate level. Transaction Level Modeling using SystemC. RTL, Test bench coding using HDL’s (VERILOG, System Verilog). Have understanding of various protocols - AHB, APB, AXI, PCIe, NVMe, Fibre Channel, RapidIO. Knowledge of ARM, PowerPC and MIPS architectures. Knowledge of SoC performance modeling.
Mirabilis Design Inc - Deepak Shankar - CEO & Co-Founder
Deepak Shankar has assisted more than 25 major agencies and aerospace companies to establish best practice in avionics system design. Mr. Shankar has been responsible for many innovations in the model-based timing and power testing for aerospace certification. He has presented these concepts at a number of IEEE, SAE and other internal conferences worldwide.